Microelectronic devices are widely used in many consumer and commercial applications. As the integration density of microelectronic devices continues to increase, it may be desirable to provide more external connectors for the microelectronic devices, to accommodate larger numbers of power supply, ground and/or input/output (I/O) signal connections.
In order to increase the number of external connectors that are available for a microelectronic device, it is known to provide a grid array microelectronic package that includes a substrate and an area array of external connectors on the substrate. As used herein, an area array of external connectors includes at least four rows and at least four columns of external connectors including a pair of peripheral rows and a pair of peripheral columns at a periphery thereof and at least one pair of interior rows and at least one pair of interior columns between the respective pair of peripheral rows and peripheral columns. By arranging external connectors over an area array rather than only at the periphery of the substrate, larger numbers of external connectors may be accommodated.
As is well known to those having skill in the art, the external connectors can include pads, pins, balls such as solder balls and/or bumps such as solder bumps, and the substrate can include an integrated circuit, a ceramic substrate, a plastic substrate, and/or a printed circuit board. Grid arrays are also referred to in the art as Ball Grid Arrays (BGA), Controlled Collapse Chip Connection (C4), flip chip, and or other designations. An overview of BGA technology may be found in Chapter E: Ball Grid Array Technology by Rörgren, of the textbook entitled “The Nordic Electronics Packaging Guideline”, 2000.
As was described above, grid array microelectronic packages can provide larger numbers of external connections for a microelectronic package. Unfortunately, however, the larger number of external connections may make it more difficult to route signal conductors, such as power supply, ground and/or I/O signal conductors, from a substrate such as an integrated circuit, ceramic substrate, plastic substrate, and/or printed circuit board to the external connectors such as pads, pins, balls, and/or bumps. As such, it is known to provide complex routing algorithms that may be used to design the routing for a grid array microelectronic package. See, for example, Global Routing for Gate Array by Li et al., IEEE Transactions on Computer Aided Design, Vol. CAD-3, No. 4, October 1984, pages 298–307 and Escape Routing Design to Reduce the Number of Layers in Area Array Packaging to Horiuchi, et al., IEEE Transactions on Advanced Packing, Vol. 23, No. 4, November 2000, pages 686–691.
U.S. Pat. No. 5,859,474 to Dordi describes a reflow ball grid array assembly wherein a first array of elongate pads is formed on a first surface, such as that of an integrated circuit substrate, and a second array of elongate pads is formed on a second surface, such as that of a printed circuit board. An array of solder balls are reflow attached to the pads of the first array and then to the pads of the second array, to thereby electrically connect the substrate to the printed circuit board. The reflow solder balls thereby conform to the elongate shapes of the pads to be configured like truncated ellipsoids. Due to the surface tension forces between the pads and the balls therebetween, the “ellipsoids” advantageously have a high standoff. Also, the pads on each of the sides of the perimeter of the array are aligned longitudinally perpendicular to the respective sides. Thereby, wide channels between adjacent elongate pads are defined, through which one or more additional traces can advantageously be routed on the surface between the pads. See the Abstract of U.S. Pat. No. 5,859,474.